 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| AZ DISPLAYS, INC. COMPLETE LCD SOLUTIONS SPECIFICATIONS FOR LIQUID CRYSTAL DISPLAY PART NUMBER: REVISED: AGM1064B Series MAY 14, 2003 General Specification Item Character Format Module Dimension Viewing Area DOT Size DOT Pitch Driving View Direction 6H o TN o LCD Type Standard Value 100X64 DOTS 34.1(W) *25.3(H) *2.0(T) 28.0(W) * 20.9(H) 0.21(W) * 0.234(H) 0.24(W) * 0.264(H) 1/64duty, 1/9bias 12Ho Other:o Table 1 Unit Dots mm mm mm mm STN Gray o STN Blue o FSTN Positive o Color STN o STN Yellow Greeno FSTN Negative o FM LCD o Reflective o Transflectiveo Display Mode Transmissive o Driver IC Interface DC/DC Converter Operation Temperature Storage Temperature 6800 o Interna l o NT7532H-TABF1 8080o 2 E Ao Externalo -10ae60ae -20ae70ae Page 1 Electronic Units 3.1 Absolute Maximum Ratings No 1 2 3 4 5 6 ITEM OPERATING TEMPERATURE STORAGE TEMPERATURE SUPPLY VOLTAGE FOR LOGIC SUPPLY VOLTAGE FOR LCD INPUT VOLTAGE STATIC ELECTRICITY Symbol T OP T ST VDD -VSS VLCD VI Min. -10 -20 VSS VSS VSS Typ. - Max. 60 70 3.6 13.5 Unit ae ae V V V - VDD+0.5 Be sure that you are grounded when handing LCM 3.2 Electrical Characteristics (Ta=25ae,VDD=3.0V) No 1 2 3 4 5 9 Item Supply Voltage For Logic Supply Voltage For LCD Driver Input High Voltage Input Low Voltage Supply Current For Logic USED IC Symbol VDD-VSS VDD-Vo (VLCD) VIH VIL IDD Condition / / H level L level / Min. / / 0.8VDD 0 / Typ. 3.0 10.0 / / / Max. / / VDD 0.2VDD 1 Uni t V V V V mA NT7532H-TABF1(NOVATEK) *Idd Measurement condition is for all pixels on display. (Unit: mA) Page 2 3.3 Interface Pin Function NO SYMBOL 1 2 3 4 NC NC NC NC Table 5 I/O Description 5 FR I/O 6 CL I/O 7 /DOF I/O This is the liquid crystal alternating current signal I/O terminal M/S = " : Output H" M/S = " : Input H" When the NT7532 chip is used in master/slave mode, the various FR terminals must be connected. This is the display clock input terminal. When the NT7532 chips are used in master/slave mode, the various CL terminals must be connected. This is the liquid crystal display blanking control terminal. M/S = " : Output H" M/S = " : Input H" When the NT7532 chip is used in master/slave mode, the various DOF terminals must be connected. 8 9 10 11 NC /CS1 NC This is the chip select signal. When CS1=" and CS2=" , then L" H" the chip select becomes active, and data/command I/O is enabled. When RES is set to " , the settings are initialized. The reset L" operation is performed by the RES signal level This is connected to the least significant bit of the normal MPU address bus, and it determines whether the data bits are data or a command. A0 = " : Indicate that D0 to D7 are display data H" A0 = " : Indicates that D0 to D7 are control data L" When connected to an 8080 MPU, this is active LOW. This terminal connects to the 8080 MPU WR signal. The signals on the data bus are latched at the rising edge of the WR signal. When connected to a 6800 Series MPU, this is the read/write control signal input terminal. When W R/ = " : Read H" When W R/ = " : Write L" When connected to an 8080 MPU, it is active LOW. This pad is connected to the RD signal of the 8080MPU, and the NT7532 data bus is in an output status when this signal is " . L" When connected to a 6800 Series MPU, this is active HIGH. This is used as an enable clock input of the 6800 series MPU This is an 8-bit bi-directional data bus that connects to an 8-bit or 16-bit standard MPU data bus. I CS2 RES I 12 A0 I 13 RD/WR I 14 E/RD I 15 D0 I/O Page 3 16 17 18 19 20 D1 D2 D3 D4 D5 When the serial interface is selected (P/S=" ), then D7 L" serves as the serial data input terminal (SI) and D6 serves as the serial clock input terminal (SCL). At this time, D0 to D5 are set to high impedance. When the chip select is inactive, D0 to D7 are set to high impedance. 21 D6SCL (c) 22 23 D7SI(c) DUTY0 Select the LCD driver duty DUTY1 DUTY1 0 0 1 0 1 LCD driver duty 1/33 1/49 1/55 1/69 I 24 DUTY1 0 1 1 25 26 27 28 29 30 31 32 33 34 35 VDD VDD2 VSS VOUT NC CAP3+ CAP1CAP1+ CAP2+ CAP2VEXT Supply each other. 2.4 - 3.5V power supply input. These pads must be connected This is the power supply for the step-up voltage circuit for the Supply LCD. These pads must be connected each other. Supply Ground output for pad option. O NC O O O O O I DC/DC voltage converter output Capacitor 3+ pad for internal DC/DC voltage converter. Capacitor 1- pad for internal DC/DC voltage converter. Capacitor 1+ pad for internal DC/DC voltage converter. Capacitor 2+ pad for internal DC/DC voltage converter. Capacitor 2- pad for internal DC/DC voltage converter. This is the external input reference voltage (VREF) for the internal voltage regulator. It is valid only when external VREF is used. VEXT must be 2.4V and VDD2. When using internal VREF, this pad must be NC. Page 4 36 37 38 39 40 VRS V1 V2 V3 V4 I Supply 41 V0 42 VR I 43 M/S I 44 CLS I 45 C86 I Select the internal voltage regulator or external voltage regulator. VRS = 0: using the external VREF VRS = 1: using the internal VREF LCD driver supplies voltages. The voltage determined by LCD cell is impedance-converted by a resistive driver or an operation amplifier for application. Voltages should be according to the following relationship: V0 = V1 = V2 = V3 = V4 = VSS When the on-chip operating power circuit is on, the following voltages are supplied to V1 to V4 by the on-chip power circuit. Voltage selection is performed by the Set LCD Bias command. LCD bias V1 V2 V3 1/5 bias 4/5V0 3/5V0 2/5V0 1/6 bias 5/6V0 4/6V0 2/6V0 1/7 bias 6/7V0 5/7V0 2/7V0 1/8 bias 7/8V0 6/8V0 2/8V0 1/9 bias 8/9V0 7/9V0 2/9V0 Voltage adjustment pad. Applies voltage between V0 and VSS using a resistive divider. This terminal selects the master/slave operation for the NT7532 chips. Master operation outputs the timing signals that are required for the LCD display, while slave operation inputs the timing signals required for the liquid crystal display, synchronizing the liquid crystal display system. Terminal to select whether enable or disable the display clock internal oscillator circuit. CLS = " : Internal oscillator circuit is enabled H" CLS = " : Internal oscillator circuit is disabled L" (requires external input) When CLS = " , input the display clock through the CL pad. L" This is the MPU interface switch terminal C86 = " : 6800 Series MPU interface H" C86 = " : 8080 MPU interface L" This is the parallel data input/serial data input switch terminal P/S = " : Parallel data input H" P/S = " : Serial data input L" The following applies depending on the P/S status: P/S "H" "L" Data/Command A0 A0 Data D0 to D7 SI (D7) Read/Write 46 P/S I RD WR Write only Serial SCL (D6) 47 /HPM I 48 IRS I When P/S = " , D0 to D5 are HZ. D0 to D5 may be " , " or L" H" L" Open. RD(E) and WR( W R/ ) are fixed to either " or " . H" L" With serial data input, RAM display data reading is not Supported. This is the power control terminal for the power supply circuit for liquid crystal drive. HPM = " , Normal mode H" HPM = " , High power mode L" This pad is enabled only when the master operation mode is selected and It is fixed to either " or " when the slave H" L" operation mode is selected. This terminal selects the resistors for the V0 voltage level adjustment. IRS = " , Use the internal resistors H" IRS = " , Do not use the internal resistors L" The V0 voltage level is regulated by an external resistive Page 5 voltage divider attached to the VR terminal. This pad is enabled only when the master operation mode is selected. It is fixed to either " or " when the slave operation mode is H" L" selected 49 NC NC 3.4 Commands The display control instructions control the internal state of the NT7532H-TABF1(NOVATEK). Instruction is received from MPU to NT7532H-TABF1(NOVATEK) for the splay control. The following table shows various instructions. *: Don' care t Command A0 RD WR D7 D6 D5 D4 Code D3 D2 D1 D0 Hex Function Display OFF 0 1 0 1 0 1 0 1 1 1 0 1 AEh AFh 40h TO 7Fh B0h to BFh 00h TO 1Fh Set Display Start Line Set Page Address 0 1 0 0 1 Display Start Address 0 0 1 1 1 0 1 0 0 0 0 1 0 1 1 0 0 0 0 0 1 0 0 1 1 0 0 Page Address Higher Column Address Lower Column Address 0 0 0 Set Column Address 0 0 1 1 Read Status Write Display Data Read Display Data ADC Select Status XX xx xx Write Data Read Data 0 1 0 1 0 1 0 1 0 0 0 0 A0h A1h Normal/Rever se Display Entire Display ON/OFF Set LCD Bias Read-ModifyWrite End 0 1 0 1 0 1 0 0 1 1 0 1 0 1 01 A6h A7h A4h A5h A2h A3h E0h 0 0 1 1 0 0 1 1 0 0 1 1 0 0 0 0 1 0 0 1 Turn on LCD panel when goes high, and turn off when goes low Specifies RAM display line for COM0 Set the display data RAM page in Page Address register Set 4 higher bits and 4 lower bits of column address of display data RAM in register Reads the status information Write data in display data RAM Read data from display data RAM Set the display data RAM address SEG output correspondence Normal indication when low, but full indication when high Selects normal display (0) or entire display on Sets LCD driving voltage bias ratio Increments column address counter during each write Releases the Read-Modify-Write Page 7 6 0 1 0 1 1 1 0 0 0 0 0 0 1 0 1 1 1 0 1 1 1 0 EEh Reset Common Output Mode Select Set Power Control V0 Voltage Regulator Internal Resistor ratio Set Electronic Volume mode Set Electronic Volume Register Set Set Static indicator ON/OFF Set Static Indicator Register Power Save 0 1 0 1 1 1 0 0 0 1 0 E2h C0h to CFh 28h to 2Fh 20h to 27h 81h XX Resets internal functions Selects COM output scan direction *: invalid data Selects the power circuit operation mode Selects internal resistor ratio Rb/Ra mode 0 1 0 1 1 0 0 0 1 * * * 0 1 0 0 0 1 0 1 Operation Status 0 1 0 0 0 1 0 0 Resistor Ratio 0 1 0 1 0 0 0 0 0 0 1 0 1 0 * * Electronic Control Value Sets the V0 output voltage electronic volume register Sets static indicator ON/OFF 0: OFF, 1: ON Sets the flash mode 0 1 0 0 0 1 0 1 0 1 0 1 ACh ADh XX 0 1 0 * * * * * * Mode 0 1 0 - - - - - - - - - NOP Test Command Test Mode Reset 0 1 0 1 1 1 0 0 0 1 1 E3h F1h to FFh F0h 0 1 0 1 1 1 1 * * * * Compound command of Display OFF and Entire Display ON Command for non-operation IC test command. Do not use! 0 1 0 1 1 1 1 0 0 0 0 Command of test mode reset Page 5 3.5 Timing Characteristics 1. System Buses Read/Write Characteristics (for 8080 Series MPU) Symbol TAH8 TAS8 TCYC8 TEWHW TEWHR TEWLW TEWLR Parameter Address hold time Address setup time System cycle time Control low pulse width (write) Control low pulse width (read) Control high pulse width (write) Control high pulse width (read) Data setup time Data hold time /RD access time Output disable time Min 0 0 300 90 120 120 60 TYP - MAX - UNIT ns ns ns ns ns ns ns Condition A0 SCL WR RD WR RD TDS8 40 ns D0~D7 TDH8 15 ns TACC8 140 ns D0~D7, CL = 100pF TOH8 10 400 ns *1. The input signal rise time and fall time (tr, tf) is specified at 15ns or less. (tr + tf) < (tCYC8 - tCCLW - tCCHW ) for write, (tr + tf) < (tCYC8 - tCCLR - tCCHR) for read. *2. All timing is specified using 20% and 80% of VDD as the reference. *3. tCCLW and tCCLR are specified as the overlap interval when CS1 is low (CS2 is high) and WR or RD is low. 2. System Buses Read/Write Characteristics (for 6800 Series MPU) Page 5 Symbol TAH6 TAS6 TCYC6 TEWHW TEWHR TEWLW TEWLR TDS6 TDH6 TACC6 TOH6 Parameter Address hold time Address setup time System cycle time Control low pulse width (write) Control low pulse width (read) Control high pulse width (write) Control high pulse width (read) Data setup time Data hold time /RD access time Output disable time Min 0 0 300 90 120 120 60 40 15 10 TYP - MAX 140 400 UNIT ns ns ns ns ns ns ns ns ns ns ns Condition A0 SCL WR RD WR RD D0~D7 D0~D7, CL = 100pF Page 5 3. Serial Interface Timing Symbol TSCYC TSHW TSLW TSAS TSAH TSDS TSDH TCSS TCSH Parameter Serial clock cycle Serial clock H pulse width Serial clock L pulse width Address setup time Address hold time Data setup time Data hold time Chip select setup time Chip select hold time Min 250 100 100 150 150 100 100 150 150 TYP - MAX - UNIT ns ns ns ns ns ns ns ns ns Condition SCL SCL SCL D/I D/I SDI SDI CS1, CS2 CS1, CS2 *1. The input signal rise time and fall time (tr, tf) is specified at 15ns or less. *2. All timing is specified using 20% and 80% of VDD as the standard. Page 5 Electro -optical Units 4.1 Electro-optical Characteristics No 1 2 Item Contrast Ratio Response time Symbol CR Tr Tf |E 1 |E 2 |E 3 Condition Ta=23 ae 3 |E 1=|E 2= |E 3=|E 4=0 Min - Typ Max Unit 5.5 260 200 60 Drive - ms ms Vop =10V 1/64 Duty Rise Down 6H |O=270 12H 3 Viewing Angle Range |O=90 3H |O=0 9H Ta=23 3ae Cr=2 - 25 Deg - 1/9 Bias f=100HZ 50 |E 4 |O=180 Ta=23 3ae - 50 V 4 LCD Driving Voltage VOP 10 Page 5 BLUE ANODE 1.MODE: FSTN-Transflective-Positive 2.1/65duty,1/9bias,view angle 6 o'clock 3.Vdd=3.0V Vlcd=10.0V 4.Operation temperature:-10aC~+60aC 5.Store temperature:-20aC~+70aC 6.Driver IC:NT7532H-TABF1 7.The tolerance unless classified A0.2 AZ Displays, Inc. AGM1064B-MLB-FBW DWG: SM5424 |
Price & Availability of AGM1064B
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |